The inventors of the present invention have examined the following technologies for a multi-processor system.
In the field of a conventional embedded microprocessor, increase in an operating frequency and improvement in a logical method have achieved both of the performance improvement and the reduction in power consumption. With the increase in the frequency of the processor, however, due to the increase in the operating power and the increase in the standby power consumption resulting from leakage current, the improvement in the operating frequency without increasing the power consumption has been approaching its limit. In such a circumstance, as means for achieving the improvement in performance of an information processing device and the reduction in power consumption thereof, a multi-processor system has shown great promise, in which a plurality of conventional processors are mounted on a chip to perform processes in parallel, thereby providing a high computing performance without increasing operating frequency.
The multi-processor system is divided into two types: symmetric multiple processor (SMP) and asymmetric multiple processor (ASMP). The SMP refers to a symmetric multi-processor having a configuration in which a plurality of processors share one OS and one memory, and the plurality of processors to be mounted are treated as equivalent and arbitrary processors execute general processes. Since the SMP can achieve the general performance improvement, it is applied to a high end server and a personal computer (PC). However, the SMP is not suited for an embedded microprocessor requiring a high real-time performance because an interrupt response time of OS adapted to the SMP is long.
Meanwhile, the ASMP refers to an asymmetric multi-processor having a configuration in which individual processors have their own memory and OS, and each of a plurality of mounted processors plays a specific role for operation. The ASMP is mainly applied to embedded microprocessors to utilize the existing software asset and to reduce the number of development processes. However, if an OS is mounted on each processor, since a memory area has to be provided for each OS process, the cost is correspondingly increased. For this reason, it is possible to provide a multi-processor system at low cost by providing a master-slave configuration including a master processor with OS and a slave processor without OS as an ASMP configuration mounted with one OS.
In order to apply the multi-processor system with such a master-slave configuration to a field of embedded equipment control in which higher real-time performance is required, a mechanism for efficiently allocating interrupt processes to each of the processors is needed. For a conventional multi-processor system with a master-slave configuration, for example, Japanese Patent Application Laid-Open Publication No. 2000-305917 (Patent Document 1) discloses a method of allocating interrupt requests so that a master processor performs a time-series process and a non-master processor performs a non time-series process.